1. Define binary logic?
Binary logic consists of binary variables and logical operations. The variables are
designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. There are three basic logic operations: AND, OR, and NOT.
The three basic logic gates are
AND gate
OR gate NOT gate
Logic gates are the basic elements that make up a digital system. The electronic gate
is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function.
Bipolar Unipolar
Saturated Non Saturated PMOS
NMOS
CMOS
RTL Schottky TTL
ECL DTL
I I L ,TTL
The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application.
The Bipolar logic family is classified into
Saturated logic Unsaturated logic.The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family.The Schottky TTL, and ECL logic comes under the unsaturated logic family.
FET is classified as
1. Junction Field Effect Transistor (JFET)
2. Metal oxide semiconductor family (MOS).
The bipolar logic family is classified as follows:
RTL- Resistor Transistor Logic
DTL- Diode Transistor logic
I2L- Integrated Injection Logic TTL- Transistor Transistor Logic ECL- Emitter Coupled Logic
Fan out
Power dissipation
Propagation Delay
Noise Margin
Fan In
Operating temperature,Power supply requirements
Fan out specifies the number of standard loads that the output of the gate can drive with out impairment of its normal operation.
Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.
Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns.
It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts.
Fan in is the number of inputs connected to the gate without any degradation in the voltage level.
All the gates or semiconductor devices are temperature sensitive in nature. The
temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c.
Some digital circuits operate in environments, which produce very high noise signals.
For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic.
1. Open collector output
2. Totem-Pole Output
3. Tri-state output.
If the channel is initially doped lightly with p-type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode.
If the region beneath the gate is left initially uncharged the gate field must induce a
channel before current can flow. Thus the gate voltage enhances the channel current and such a device is said to operate in the enhancement mode.
1. The n- channel MOS conducts when its gate- to- source voltage is positive.
2. The p- channel MOS conducts when its gate- to- source voltage is negative
3. Either type of device is turned of if its gate- to- source voltage is zero.
A schottky diode is formed by the combination of metal and semiconductor. The
presence of schottky diode between the base and the collector prevents the transistor from
going into saturation. The resulting transistor is called as schottky transistor.
The use of schottky transistor in TTL decreases the propagation delay without a
sacrifice of power dissipation.
1.TTL (Std.TTL) 2.LTTL (Low Power TTL)
3.HTTL (High Speed TTL) 4.STTL (Schottky TTL)
5.LSTTL (Low power Schottky TTL)
Totem pole outputs cannot be connected together because such a connection might produce excessive current and may result in damage to the devices.
Adv: Easily compatible with other ICs
Low output impedance
Disadv: Wired output capability is possible only with tristate and open collector types Special circuits in Circuit layout and system design are required.
When noise voltages are within the limits of VNA(High State Noise Margin) and VNK for a particular logic family.
It is the oldest and standard CMOS family. The devices are not pin compatible or
electrically compatible with any TTL Series.
Unit – II
When logic gates are connected together to produce a specified output for certain
specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.
The problem definition
Determine the number of available input variables & required O/P variables.
Assigning letter symbols to I/O variables
Obtain simplified Boolean expression for each O/P.Obtain the logic diagram.
The logic circuit that performs the addition of two bits is a half adder. The circuit that performs the addition of three bits is a full adder.
A decoder is a multiple - input multiple output logic circuit that converts codedinputs into coded outputs where the input and output codes are different.
A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n out puts lines.
An encoder has 2n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input value.
A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence.
Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line.
A comparator is a special combinational circuit designed primarily to compare the relative magnitude of two binary numbers.
. Read only memory . Programmable logic Array . Programmable Array Logic
A read only memory(ROM) is a device that includes both the decoder and the OR
gates within a single IC package. It consists of n input lines and m output lines. Each bit
combination of the input variables is called an address. Each bit combination that comes out
of the output lines is called a word. The number of distinct addresses possible with n input variables is 2n.
In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word.
. Masked ROM.
. Programmable Read only Memory
. Erasable Programmable Read only memory.. Electrically Erasable Programmable Read only Memory.
41. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept;however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.
42. Which gate is equal to AND-invert Gate?
NAND gate.
NOR gate.
NAND gate
NOR gate
PROM (Programmable Read Only Memory)
It allows user to store data or program. PROMs use the fuses with material
like nichrome and polycrystalline. The user can blow these fuses by passing
around 20 to 50 mA of current for the period 5 to 20µs.The blowing of fuses is
called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent.
EPROM(Erasable Programmable Read Only Memory)
EPROM use MOS circuitry. They store 1’s and 0’s as a packet of charge in a
buried layer of the IC chip. We can erase the stored data in the EPROMs by
exposing the chip to ultraviolet light via its quartz window for 15 to 20
minutes. It is not possible to erase selective information. The chip can bereprogrammed.
48. Explain EEPROM.
EEPROM also use MOS circuitry. Data is stored as charge or no charge on an
insulated layer or an insulated floating gate in the device. EEPROM allows
selective erasing at the register level rather than erasing all the information
since the information can be changed by using electrical signals.
49. What is RAM?
Random Access Memory. Read and write operations can be carried out.
In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept;however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.
With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.
52. What is field programmable logic array?
PLA: Both AND and OR arrays are programmable and Complex
Costlier than PAL
PAL
AND arrays are programmable OR arrays are fixed Cheaper and Simpler
Programmable Logic Devices consist of a large array of AND gates and OR gates that can be programmed to achieve specific logic functions.
PLDs are classified as PROM(Programmable Read Only Memory), ProgrammableLogic Array(PLA), Programmable Array Logic (PAL), and Generic Array Logic(GAL)
PROM is Programmable Read Only Memory. It consists of a set of fixed AND gatesconnected to a decoder and a programmable OR array.
PLA is Programmable Logic Array(PLA). The PLA is a PLD that consists of aprogrammable AND array and a programmable OR array.
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.
It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.
The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.
PAL - Programmable Logic Array
10 - Ten inputs
L - Active LOW Ouput
8 - Eight Outputs
62.Give the comparison between PROM and PLA.
1. And array is fixed and OR Both AND and OR arrays are
array is programmable. Programmable.
2. Cheaper and simple to use. Costliest and complex than
PROMS.
63. What are the classification of sequential circuits?
The sequential circuits are classified on the basis of timing of their signals into two
types. They are,
1)Synchronous sequential circuit.
2)Asynchronous sequential circuit.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.
There are various types of flip flops. Some of them are mentioned below they are,
RS flip-flop
SR flip-flop
D flip-flop
JK flip-flop
T flip-flop
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.
• When K input is low and J input is high the Q output of flip-flop is
set.
• When K input is high and J input is low the Q output of flip-flop is
reset.
• When both the inputs K and J are low the output does not change
• When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.
T flip-flop is also known as Toggle flip-flop.
• When T=0 there is no change in the output.
• When T=1 the output switch to the complement state (ie) the outputtoggles.
69. Define race around condition.
change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called ‘race around condition’.
The problem of race around condition can solved by edge triggering flip flop. The
term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.
The time required to change the voltage level from 10% to 90% is known as rise time(tr).
The time required to change the voltage level from 90% to 10% is known as fall time(tf).
The phase shift between the rectangular clock waveforms is referred to as skew and the time delay between the two clock pulses is called clock skew.
The setup time is the minimum time required to maintain a constant voltage levels at
the excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as tsetup.
The hold time is the minimum time for which the voltage levels at the excitationinputs must remain constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as thold .
A propagation delay is the time required to change the output after the application of the input.
A register is a group of flip-flops flip-flop can store one bit information. So an n-bit register
has a group of n flip-flops and is capable of storing any binary information/number containing n-bits.
The binary information in a register can be moved from stage to stage within the
register or into or out of the register upon application of clock pulses. This type of bit
movement or shifting is essential for certain arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers.
There are five types. They are,
Serial In Serial Out Shift Register
Serial In Parallel Out Shift Register
Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift Register ,,Bidirectional Shift Register
RS flip-flop
In RS flip-flop there are four possible transitions from the present state to the
next state. They are,
00 transition: This can happen either when R=S=0 or when R=1 and
S=0.
01 transition: This can happen only when S=1 and R=0.
10 transition: This can happen only when S=0 and R=1.
11 transition: This can happen either when S=1 and R=0 or S=0 and
R=0.
In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables.
Combinational circuits Sequential circuits
Memory unit is not required Memory unity is required Parallel adder is a combinational circuit Serial adder is a sequential circuit
The information stored in the memory elements at any given time define.s the present state of the sequential circuit.
The present state and the external inputs determine the outputs and the next state ofthe sequential circuit.
86. State the types of sequential circuits?
2. Asynchronous sequential circuits
In synchronous sequential circuits, signals can affect the memory elements only at
discrete instant of time.
88. Define Asynchronous sequential circuit?
In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.
Synchronous sequential circuits Asynchronous sequential circuits.
Memory elements are clocked flip-flops Memory elements are either unlocked flip -
flops or time delay elements.Easier to design More difficult to design
waveform Assume initially Q = 1
Here the latch input has to be pulsed momentarily to cause a change in the latch output state, and the output will remain in that new state even after the input pulse is over.
In the JK latch, the output is feedback to the input, and therefore changes in the output
results change in the input. Due to this in the positive half of the clock pulse if J and K are
both high then output toggles continuously. This condition is known as race around condition.
Asynchronous counters Synchronous counters
In this type of counter flip-flops are
connected in such a way that output of 1st
flip-flop drives the clock for the next flipflop.
In this type there is no connection between
output of first flip-flop and clock input of
the next flip - flop
All the flip-flops are Not clocked
simultaneously
All the flip-flops are clocked simultaneously
MOD - 32 ripple counter f max (ripple) = 5 x 50 ns = 4 MHZ]
-present state variables in asynchronous sequential circuits
-next state variables in asynchronous sequential circuits
-input variables changes if the circuit is stable
-inputs are levels, not pulses
-only one input can change at a given time
97. What are pulse mode circuit?
-width of pulses are long for circuit to respond to the input
-pulse width must not be so long that it is still present after the new state is reached
In synchronous circuits-state assignments are made with the objective of circuit
reduction Asynchronous circuits-its objective is to avoid critical races
-two or more binary state variables change their value in response to the change in i/p variable
-final stable state does not depend on the order in which the state variable changes
-race condition is not harmful
-final stable state depends on the order in which the state variable changes
-race condition is harmful
-asynchronous circuit makes a transition through a series of unstable state
-shared row state assignment
-one hot state assignment
-construction of primitive flow table
-reduction of flow table
-state assignment is made
-realization of primitive flow table
-unwanted switching transients
-output goes momentarily 0 when it should remain at 1
-output goes momentarily 1 when it should remain at 0
-output changes 3 or more times when it changes from 1 to 0 or 0 to 1
-unequal delays along 2 or more path from same input
-state table of an synchronous sequential network
-one stable state per row
Output depends on the given input. It has no storage element.
The merger graph is defined as follows. It contains the same number of vertices as the
state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn.
A Set of compatibles is said to be closed if, for every compatible contained in the set,all its implied compatibles are also contained in the set. A closed set of compatibles, which contains all the states of M, is called a closed covering.
For the design of sequential counters we have to relate present states and next states.The table, which represents the relationship between present states and next states, is called state table.
The combination of level signals that appear at the inputs and the outputs of the delays define what is called the total state of the circuit.
1. Construction of a primitive flow table from the problem statement.
2. Primitive flow table is reduced by eliminating redundant states using the state reduction
3. State assignment is made
4. The primitive flow table is realized using appropriate logic elements.
It is defined as a flow table which has exactly one stable state for each row in the
table. The design process begins with the construction of primitive flow table.
1. Fundamental mode circuits
2. Pulse mode circuits
asynchronous circuit.
In synchronous circuit, the state assignments are made with the objective of circuit
reduction. In asynchronous circuits, the objective of state assignment is to avoid critical races.
121.What are races?
an input variable, race condition occurs in an asynchronous sequential circuit. In case of
unequal delays, a race condition may cause the state variables to change in an unpredictable manner.
If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race.
If the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race.
A cycle occurs when an asynchronous circuit makes a transition through a series ofunstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable to another, until the inputs are changed.
Fundamental mode circuit assumes that. The input variables change only when the circuit is stable. Only one input variable can change at a given time and inputs are levels and not pulses.
Pulse mode circuit assumes that the input variables are pulses instead of level. The width of the pulses is long enough for the circuit to respond to the input and the pulse width must not be so long that it is still present after the new state is reached.
The delay elements provide a short term memory for the sequential circuit. The present state and next state variables in asynchronous sequential circuits are called secondary variables.
128. Define flow table in asynchronous sequential circuit.
In asynchronous sequential circuit state table is known as flow table because of the behaviour of the asynchronous sequential circuit. The stage changes occur in independent of a clock, based on the logic propagation delay, and cause the states to .flow. from one to another.
129. A pulse mode asynchronous machine has two inputs. If produces an output whenever two consecutive pulses occur on one input line only. The output remains at 1 until a pulse has occurred on the other input line. Write down the state table for the machine.
A transition from one stable state to another occurs only in response to a change in the
input state. After a change in one input has occurred, no other change in any input occurs
until the circuit enters a stable state. Such a mode of operation is referred to as a fundamental mode.
Races can be avoided by making a proper binary assignment to the state variables.Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which transitions occur be given adjacent assignments. Two binary are said to be adjacent if they differ in only one variable.
The one hot state assignment is another method for finding a race free state
assignment. In this method, only one variable is active or hot for each row in the original
flow table, ie, it requires one state variable for each row of the flow table. Additional row are introduced to provide single variable changes between internal state transitions.
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